One of the challenges facing broad commercialization of nanotube technology is the lack of a clear path for integrating carbon nanotubes (CNTs) with standard CMOS devices. There have been prior attempts to use nanoelectromechanical switches (NEMS) for non-volatile memory applications where such nanotube-based NEMS devices were fabricated in a silicon manufacturing plant using standard fabrication equipment. However, such prior silicon fabrication approaches of manufacturing NEMS or CNT-based switches did not integrate CNT devices with silicon CMOS devices on the same wafer.
There have also been attempts at integrating nanotube FETs with nMOS (n-channel metal oxide semiconductor) technology. However, such integration techniques with nMOS processes deviated from standard CMOS processes having both nMOS and pMOS (p-channel metal oxide semiconductor) regions and required deep poly backside gate contacts and buried, under-oxide, source/drain regions. Such techniques for integrating CNT devices with an nMOS flow were uniquely tailored to CNT device fabrication and quite different from the standard CMOS process technology.